1. Field of the Invention
This invention relates to flash memories, and, more particularly, to a flash memory having a charge-trapping layer formed by implanting arsenic into ZrON.
2. Description of Related Art
According to International Technology Roadmap for Semiconductors (ITRS), the degraded endurance and retention are the toughest challenges to further down-scaling the Charge-Trapping Flash (CTF), due to the fewer electrons stored in highly scaled device. On the other hand, scaling down the Si3N4 charge-trapping layer to 3-4 nm is needed in ITRS for continuous device scaling, but no proposed solution up to now. However, this worsens the retention and endurance due to the poorer trapping capability at thinner Si3N4, where nearly no charge trapping was found in 2 nm Si3N4. Although the retention is improved by using a thicker tunnel oxide, this yields reduced erase speed. Such retention and erase-speed trade-off is a basic limitation of CTF.
Previously we addressed this limitation with a deep trapping energy Evac−EC Al(Ga)N or HfON in a metal-oxide-nitride-oxide-Si (MONOS) device. The better retention of high-κ Al(Ga)N MONOS CTF was also listed in ITRS. One drawback of desired higher κ HfON is the lower trapping efficiency; thus, the double trapping HfON—Si3N4 CTF was used. Yet the scaling equivalent-Si3N4-thickness (ENT) is still limited to 7 nm.